Dr. S Subba Rao

Dr. S Subba Rao,

Assistant Professor,

Department of Electronics and Communication Engineering,

IIITDM Kurnool.


Education Qualifications:

  • Ph. D (2017-2021) in Semiconductor device modeling and simulation, NIT Warangal.
  • M. Tech (2006-2008) in Electronics Design and Technology, NIT Calicut.
  • B. Tech (2001-2005) in ECE, GPREC, Kurnool, AP.

 Areas of Interest/Specialization:

  • Semiconductor device modeling and simulation, Analog IC design, Digital IC design, and Mixed signal IC design.

Academic Achievements:

  • Qualified GATE in 2006 with all India rank 2828   

Experience:

  • Assistant Professor-Grade II in ECE Department, IIITDM Kurnool, from 17th March 2023 to till date.
  • Assistant Professor in ECE Department, Vasavi college of Engineering, Hyderabad from 30th August 2021 to 16th March 2023.
  • Assistant Professor in ECE Department, V R Siddhartha Engineering College, Vijayawada from 16th June 2008 to 22nd July 2017.


Publication Profiles:

Funded Consultancy Project:

Investigator: Verification of ANURAG Processor Core (9.5 lakhs), ANURAG Labs, DRDO (January 2012 – February 2013).

Publications: (https://scholar.google.com/citations?hl=en&user=jgEMw7YAAAAJ&view_op=list_works&sortby=pubdate)  

S Subba Rao and N. Bheema Rao, “A Center Potential based Threshold Voltage Model for Graded-Channel Dual-Material Double Gate Strained-Si MOSFET with Interface Charges”, Journal of Computational Electronics, Vol. 18, Issue 4, pp. 1173–1181, 2019. (SCIE-Springer)

S Subba Rao and N. Bheema Rao, “Analytical modeling of subthreshold current and swing of strained-Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance” International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Vol. 34, Issue 1, 2021. (SCI- Wiley)

S Subba Rao and N. Bheema Rao, “Analog/RF performance of strained-Si Graded Channel Dual Material Double Gate MOSFET with interface charges” Journal of Computational Electronics, Vol. 20, Issue 1, pp. 492-502, 2021. (SCIE-Springer)

S Subba Rao and N. Bheema Rao, “Analog/RF performance of Graded Channel Gate stack Triple Material Double Gate strained-Si MOSFET with fixed charges” Silicon, Vol. 14, Issue 6, 2741–2756, 2022. (SCIE-Springer)

Sandeep M, Ramesh L, S Subba Rao, S Gopi Krishna, “Investigation of Subthreshold Characteristics of Negative Capacitance Single-Active Layer Double-Gate (NC-SALDG) Thin-Film Transistor (TFT)”, Silicon, Vol. 14, Issue 3, 1309–1314, 2022. (SCIE-Springer)

S Subba Rao and N. Bheema Rao, “Variability analysis of strained-Si Graded Channel Dual Material Double Gate MOSFET with interface charges” Journal of Computational Electronics, Vol. 21, Issue 1, pp. 243-252, 2022. (SCIE-Springer)

S Subba Rao, Rani Deepika B J, Vijaya Durga C, Gopi Krishna S, D. Srikar, and N. Bheema Rao, “Analog/RF performance of Graded Channel Gate stack Triple Material Double Gate Junction less strained-Si MOSFET with fixed charges” Silicon, Vol. 14, 7363–7376, 2022. (SCIE-Springer)

Vijaya Durga Chintala, S. Subba Rao and Anuradha Sundru, “Performance Analysis of Hybrid Transform for Universal Filtered Multi Carrier System” Transactions on Emerging Telecommunications Technologies, vol. 33, no.12, e4644, 2022. (SCIE-Wiley). 

Conferences:

Swapna Sarker, S Subba Rao and N. Bheema Rao, “Simulation and Performance Analysis of Hetero Dielectric Underlap Asymmetrical Double-Gate MOSFET Using Gate Stack”, INDICON, 2021, pp. 1-6, doi: 10.1109/INDICON52576.2021.9691765.

Seminars / Workshops Attended:

Attended one week CEP course on “Semiconductor Technology & Manufacturing” held during 10th to 15th December 2013 organized by department of Electrical department, IIT Bombay, Mumbai.

Attended one week QIP course on “Electromagnets in VLSI” held on 16th to 21st June 2014, organized by department of ECE, NIT Calicut, Calicut.

Attended one week short term course on “Emerging technologies: Electronic devices & Materials” held during 01st to 4th October 2014 organized by the department of ECE, MNIT Jaipur, Jaipur.

Attended a three day 4th INUP Familiarization Workshop during December 16-18, 2015 organized by the department of Electrical engineering, IIT Bombay, Mumbai.

Attended two week GIAN course on “Modeling, Simulation and Characterization of Nano-Transistors” held during 13th to 24th October 2015 organized by the department of Electrical engineering, IIT Kanpur, Kanpur.

Attended one week short term course on “Charge and Spin Based Electronics: From Devices to Circuits and Systems” held during 26th to 30th June 2016 organized by the department of ECE, IIEST Shibpur, Kolkata.

Attended one week FDP on “VLSI Devices and Technology” during October 3rd-8th, 2017 organized by the department of Electrical engineering, IIT Roorkee.

Attended one week GIAN program on “Advanced CMOS clock generation circuits”, during 25th to 29th December 2017 organized by the department of ECE NIT Warangal.

Volunteered and participated in IC2SV2019 international conference during 23rd to 24th 2019 organized by the department of ECE NIT Warangal.

Subject handled:

  1. Electronic devices and circuits,
  2. Pulse & switching circuits,
  3. VLSI design,
  4. Integrated circuits & applications,
  5. Digital logic design,
  6. Analog integrated circuit design,
  7. Digital integrated circuit design,
  8. Semiconductor device modeling,
  9. Low power VLSI design. 

Other Responsibilities:

  • Hostel warden (MVH), IIITDM Kurnool, from March 2022 onwards. 

Contact:

Email: ssr29@iiitk.ac.in

Office: 08518-289109